Japanese Laid-open Patent Publication No. 2007-258541 describes a wiring substrate including an electronic component such as a semiconductor chip. The wiring substrate includes a planar core and build-up layers formed on upper and lower surfaces of the core. A through hole extends through the core. An electronic component is arranged in the through hole. The through hole is filled with an insulator such as a resin. A via formed in each build-up layer electrically connects the electronic component to a wire in the build-up layer.
When manufacturing the wiring substrate, heat is applied to the core, the insulator filled in the through hole of the core, and the electronic component arranged in the through hole of the core. However, each of these members has a different coefficient of thermal expansion. This may deform the build-up layers. Such deformation of the build-up layers may lead to defects such as cracking or defoliation of the build-up layers or wire breakage.